An Efficient Timing Closure Methodology in ASIC ECO Step
Youngho Seo, Hyun‐Jun Choi, Jisang Yoo, Dong-Wook Kim · The Journal of the Korean Institute of Information and Communication Engineering · 2009
In this paper, we propose an efficient methodology to fix timing violation in ECO step for ASIC process. Timing violation can occur from various reasons and the major cause is inconsistent correlation between EDA tools. The most frequent violation is setup time and hold time violation. First, we analyzed the reason of violation creation, and then proposed the adjusting method for overcome them. Each violation can be fixed by increasing data required time or decreasing data arrival time. We proposed the detailed technique on a case basis. It is difficult to execute these methods by routine of algorithm or principle. Therefore ASIC engineer needs to apply these technique to violation as conditions of the implemented design.