Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation
Yi‐Hsuan Hsiao, Hang-Ting Lue, Wei-Chen Chen, Bing‐Yue Tsui, Kuang-Yeu Hsieh, Chih-Yuan Lu · IEEE Electron Device Letters · 2015
Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry.