A cost effective way to test embedded RAM and ROM
G. Van Wauwe, E. Huyskens · Third Annual IEEE Proceedings on ASIC Seminar and Exhibit · 2002
A method to handle the testability of a variety of RAM and ROM structures with a self test is proposed. Coverage can be determined as a direct function of the test sequence length, and is sufficient for all present cases. The test cases show that this approach is most cost-effective for the RAM and ROM modules under consideration. Silicon overhead is kept low due to the maximal reuse of the functional logic. The resulting tester patterns require negligible tester memory.>