Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Richard Kimura, Hironori Kasahara · 2005
Abstract. With the advance of semiconductor technology, chip multiprocessor architectures, or multi core processor architectures have attracted much attention to achieve low power consumption, high effective performance, good cost performance and short hardware/software development period. To this end, parallelizing compilers for chip multiprocessors are expected that allow us to parallelize program effectively and to control the voltage and clock frequency of processors and storages carefully inside an application program. This paper proposes parallelizing compilation scheme with power reduction control under the multigrain parallel processing environment that controls Voltage/Frequency and power supply of each processor core on a chip. In the evaluation, the OSCAR compiler with the proposed scheme achieves 60.7 percent energy reduction for SPEC CFP95 applu without performance degradation on 4 processors, and 85.6 percent energy reduction for SPEC CFP95 tomcatv with real-time deadline constraint on 4 processors, and 86.7 percent energy reduction for SPEC CFP95 swim with the deadline constraint on 4 processors. 1