An efficient memory-based FFT architecture
Chao-Kai Chang, Chung-Ping Hung, Sau-Gee Chen · 2003
This paper proposes an efficient memory-based radix-2 FFT architecture, which greatly improves the memory-based FFT by reducing 50% memory size requirement, while maintaining a simple address generator. Specifically the memory size is reduced to 1.25N words. In addition, the multiplier utilization rate is 100%.