A 15 nanosecond complex multiplier-accumulator for FFTS
Robert E. Owen · 2005
A recently announced bipolar fabrication process provides VLSI densities of high-speed ECL gates with substantially lower power dissipation. A multiplier-accumulator and multi-port register file have been produced with this process with worst-case cycle times of 15-nanoseconds. This paper describes the use of this complex multiplier-accumulator's new architectural features and speed with the register file to do high bandwidth fast Fourier transforms in a variety of different configurations.