Circuit architectures for semi-bit-serial and programmable arithmetic in finite fields
Robert W. Furness, Mohammed Benaissa, S.T.J. Fenn · 2002
In this paper we present semi-bit-serial and programmable circuit architectures for performing arithmetic in GF(2/sup m/). The semi-bit-serial mathematical architectures offer a structure that operates faster than traditional bit-serial architectures, whilst offering considerably lower hardware requirements than a bit-parallel architecture. This new approach to arithmetic operations in GF(2/sup m/) is based on composite fields of the form GF((2/sup n/)/sup 2/) (m=2n). It is also shown that these operators lend themselves to programmable architectures that operate in either GF(2/sup m/) or GF(2/sup n/). The circuit architectures proposed in this paper support implementation in VLSI systems due to their regular and hardware efficient circuit structures and are therefore suited to use in Reed-Solomon error-correction codecs.