A VLSI design for full search block matching motion estimation
Seung Hyun Nam, Jong Seob Baek, Tae Young Lee, Moon Key Lee · 2002
In this paper, we describe a flexible VLSI architecture to achieve a real-time processing of full-search block matching algorithm (FBMA) for video applications. The proposed architecture uses a parallel algorithm based on the idea of partial result accumulation. The partial sum results of the candidate block distortions are individually accumulated into cyclic storage buffer for each distortion measure. A parameterizable Motion Estimation Processor (MEP) is designed for both different reference block sizes and various search ranges. Moreover, for larger search ranges and high throughput rates, multiple number of MEPs can be cascaded. It has serial data input but performs parallel processing. It can be easily and cost-effectively implemented into VLSI by its simple one dimensional semi-systolic array architecture and control.>