Interfacing multiple processors in a system-on-chip video encoder
Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka P. P. Saarinen · 2002
Interfacing RISC and DSP processors as Intellectual Property blocks for an MPEG-4 baseline video encoder is presented. Our previously presented Heterogeneous IP Block Interconnection (HIBI) architecture is used as a base for contemporary System-on-Chip implementations. Cost effective, general-purpose processor cores and DSPs lacking a native HIBI support need very low-delay interfacing units that are explained in detail in this paper. Interfaces are written in synthesisable VHDL and verified in Mentor Seamless CVE co-verification environment.