Comparing Subtraction-Free and Traditional AMI
Jiří Buček, Róbert Lórencz · 2006
This paper presents FPGA implementations of traditional almost Montgomery inverse and subtraction-free almost Montgomery inverse and compares their space and time properties. The subtraction-free algorithm with its hardware architecture overcomes the disadvantages of currently known methods (e.g. Gutub, et al., 2002). The ">" or "<" tests that require either extra clock cycles or extra chip area are completely eliminated.