A dynamic algorithm to reduce power consumption in multi-core processors
Rahul Ravichandran, Vignesh Muralidharan · 2015
The usage of multi-core processors has increased exponentially in the past decade. The need of the hour is to optimize the power and performance of a chip multi-core processor (CMP). In this paper, we propose a dynamic algorithm to improve power efficiency of a CMP using pipeline stage unification (PSU) and dynamic voltage frequency scaling (DVFS). The proposed algorithm alters various parameters like clock frequency, supply voltage, number of active cores, etc dynamically to obtain the best power-performance ratio.