Selective optimization of test for embedded flash memory
R. Barth · 2003
Testing of embedded flash can be performed cost effectively in a high volume commodity environment assuming a) the chip is designed to support DAT (direct access test) for flash; b) the design supports full structural scan and boundary scan test; c) the tester supports flash memory test and scan test; and d) the tester can run concurrent scan/boundary scan test and memory test to make use of long flash test time.