Register-based multi-port perfect shuffle networks
Tuomas Järvinen, Jarmo Takala, David Akopian, Jukka P. P. Saarinen · 2002
Perfect shuffle permutation can be found in several digital signal processing algorithms. When realizing such algorithms with parallel array processor architectures, a multi-port network performing the perfect shuffle reordering is needed. In this paper, three different multi-port perfect shuffle networks are presented in general form. The networks are based on the principal decomposition of perfect shuffle permutation, where the complete reordering can be realized with a static, hard-wired part and a dynamic, register-based part. In addition, estimations of the synthesized networks are given in terms of network area and delay.