VSDF: synchronous data flow for VLSI
A. Kerihuel, R. McConnell, Sanjay V. Rajopadhye · 2002
This article describes a modified Synchronous Data Flow (SDF) model which is suitable for modeling synchronous VLSI circuits. The target model takes advantage of the synchronous nature of the operations to eliminate buffering between circuits where possible. We introduce a temporal notation, and define relevant functions for constructing a system.