Time domain approach for the evaluation of RC delays effects in ULSI interconnect lines
Loris Vendrame, Luca Bortesi, M. Biasio, Gaudenzio Meneghesso · 2005
The evaluation of RC effects in ULSI technology is important both for process development and for accuracy verification of back-end modeling and cad-tools. The paper proposes a new methodology with one possible implementation for the measurement of RC delays in ULSI interconnect lines (DUT). The proposed implementation has been developed at wafer level by means of a mid-complexity test circuit whose working principle is based on the comparison between the RC delay of the DUT and a well-known reference delay generated on-chip.