An implementation of the Zer o Instruction Set Computer (ZISC036) on a PC/ISA-bus card
Age J. Eide, Thomas Lindblad, Clark S. Lindsey, A. Minerskjold, G. Sekhniaidze, Géza Székely · 1994
: An implementation of the new IBM Zero Instruction Set Computer (ZISC036) on a PC/ISA-bus card is reported. This circuit has 36 processing elements of a type similar to that of Radial Basis Function or RBF-like neurons. It is a highly parallel and cascadeable building block with on-chip learning capability, and is well suited for pattern recognition, signal processing, etc. A card with two ZISC036 was built and tested with a noisy character recognition "benchmark". Some future implementations and ideas are presented. 1. Introduction We describe the first implementation of the IBM Zero Instruction Set Computer (ZISC036) on a PC-486 ISA-bus card. This chip has a RBF-like [1-2] neural network topology and a RCE learning algorithm embedded on-chip [3]. Although this learning concept involves simple commitment of trainingvectors(usuallycalledprototypes)tomemoryandadjustmentofscalarweighting factors, such networkshavebeenshowntodefine classification boundariesofcomplicatedclusteringinmult...