A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture
Lingzhi Liu, Lin Qiu, Rong Meng-tian, Li Jiang · IEEE International Workshop on System-on-Chip for Real-Time Applications · 2004
A design of 2-D forward and inverse integer transform processor is presented, which is suitable for MPEG-4 AVC/H.264 visual profile. The comparability between the forward and inverse transform and the symmetry of their arithmetic has been utilized in architecture. According to this design, 2-D transform is implemented by using duplicated 1-D transform. Parallel register array are used to realize the transpose operation. Under 0.35um technology, the logic gate count is only 3524 when the maximum frequency is more than 120MHz.