50,000 gate ASIC prototyping PLD using four flex 8000 devices and a programmable interconnect
R. Terrill · 2002
Gate array designs are usually simulated to catch logic errors prior to silicon production. Emulation, or implementation and testing of the custom design in reprogrammable hardware, provides more exhaustive evaluation of design accuracy, but most hardware emulation systems are large and expensive. This paper presents a 50,000-gate programmable logic device (PLD) that has been developed to support medium density gate array emulation inexpensively, and in a small form-factor.>