Digital Implementation of a Single Dynamical Node Reservoir Computer
Miquel L. Alomar, Miguel C. Soriano, M. Escalona-Morán, Vincent Canals, Ingo Fischer, Cláudio R. Mirasso, Josep L. Rosselló · IEEE Transactions on Circuits & Systems II Express Briefs · 2015
Minimal hardware implementations of machine-learning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements and FPGA properties, namely, parallelism and adaptation. Here, we present an FPGA implementation of a conceptually simplified version of a recurrent NN based on a single dynamical node subject to delayed feedback. We show that this configuration is capable of successfully performing simple real-time temporal pattern classification and chaotic time-series prediction.