Boundary scan modification to enhance multichip module testing
J.M. Aubert · 2003
A boundary scan modification enables a single scannable application specific memory interface to test interconnects for stuck-at-zero faults and shorts on control, address, and data signal paths to memory devices without boundary scan capability. Texas Instruments used extensive boundary scan embedded testing, via IEEE 1149.1, for design verification and test of the gigabit memory unit (GMU) used in the solid-state recorder (SSR). The GMU utilized multichip module technology to provide 1.2 Gb of memory in 10 in/sup 3/ while using only 1.4 W of power. These applications required one of the first implementations of boundary scan in field programmable gate arrays (FPGAs). The program demonstrated that successful multichip module design and test requires boundary scan capability.>