Architecture and Implementation of PIM/m.
Hiroshi Nakashima, Katsuto Nakajima, Seiichi Kondo, Yasutaka Takeda, Yu Inamura, Satoshi Onishi, Kanae Masuda · 1992
In the FGCS project, we have developed a parallel inference machine, PIM/m, as one of the final products of the project. PIM/m has up to 256 processor elements (PEs) connected by a 16 2 16 mesh network, while its predecessor, Multi-PSI/v2, has 64 PEs. A PE has three custom VLSI chips, one of which is a pipelined microprocessor having special mechanisms for KL1 execution, such as pipelined data typing and dereference. As for the KL1 implementation on PIM/m, we took much care of garbage collection and introduced various techniques, such as incremental reclamation of local and remote garbage. Especially, a hardware mechanism to support the local garbage collection greatly contributes to reducing the overhead and achieving high peak performance, 615 KLIPS in append on single processor. Sustained performance of single processor is also improved, and is approximately twice as high as that of Multi-PSI/v2. This improvement and the enlargement of the system scale cooperatively enhance the tota...