Systolic Design with Asynchronous Controls for Digital-Signal Processing
Kamran Reihani · Defense Technical Information Center (DTIC) · 1993
The research sponsored by this grant is focused on the development of a theoretical and technological basis for designing efficient systolic arrays for digital-signal processing algorithms. The major contributions of the research are the following: Data reduction techniques via the utilization of algorithm properties Conversion of sequential input signal into input blocks by means of a spiral systolic mesh that is suitable for parallel processing and that is flexible for enabling various array dimensions Devising a hybrid of SA and data-flow approach, making data streams independent of computations executed in each processor, thus reducing waiting time. The communication (PE) protocols resolve the data-flow conflicts created by the merging of the spiral and asynchronous systolic array architecture.