Design and implementation of high speed code extractor
Chen Guican, Jun Cheng, Xiao-Yan Tang · 2002
By taking an example of using Xilinx FPGA device to implement the high speed code extractor we introduce a way to meet the time constraints of the demands of the high speed circuit in the phase of the schematic design. We employ global buffers using flip-flop location and using TIMESPEC component in the schematic design to implement a design that operates at high frequency (52 MHz) successfully and easily.