CMOS VLSI implementation of a digital logarithmic multiplier
Srinath M. Ramaswamy, R. Siferd · 2002
A fast multiplier based on the logarithmic number system is implemented in a VLSI chip. Multiplication in the decimal number system is equivalent to an addition in the logarithmic number system, thus, the use of logarithms reduce the operation of multiplication to simple addition. Multiplication of two binary numbers can be achieved by adding the binary logarithms of the two numbers and then deriving the antilog of the result. The approximate logarithm of a binary number can be found from the number itself through a process of shifts and counting. This is a simpler design process as compared to storing the logarithms on an on-chip ROM which results in complex hardware as the word length increases. The logarithmic approximation results in some error in the product. This is reduced using an error reduction technique. The presence of error limits the application of this multiplier to applications in signal processing where it is not critical. The design is implemented using a 2.0 micron double metal process.