A 54 MHz chip set for HDTV filtering
C. Joanblanq, Frédéric Rothan, P. Senn · 2002
The HDTV European project EUREKA-95 requires complex video processing to be carried out in the encoder. A chip set optimized for large kernel 2D transversal filters, including a programmable delay line and a filter chip, is presented. They can operate at 54 MHz and have been developed in a 1.0 mu m CMOS technology. The basic architecture is a modified transposed transversal filter systolic array, where an extra data bus and a 9-b adder are provided in each filter cell to handle the horizontal symmetry. Though expensive compared to a folded data bus, this structure can be pipelined to relax the timing demands for high-speed applications.>