Fault-tolerance design of memory systems based on DBL structures
Chih-Hsien Hsu, Shyue-Kung Lu · Asia Pacific Conference on Circuits and Systems · 2003
This paper is based on the concept of divided bitline (DBL) structures for high capacity memories. The DBL approach has been proposed for low-power memory design. However, the characteristics of the DBL structure have not been used for fault-tolerant memory (FTM) systems. Therefore, we propose the column block-based fault-tolerant memory (CBFTM) system based on the DBL structure. Normal (and redundant) columns of a memory array are divided into column blocks, i.e. the reconfiguration is performed at the column block level instead of the traditional. column level. The reconfiguration mechanism of our CBFTM system requires less hardware overhead for high capacity memories. We also compare the repair rate between our CBFTM approach and the column-based FHFR (first-hit-first-repair) algorithm. It also concludes that our CBFTM approach can improve repair rate significantly.