Performance analysis of low power microcode based asynchronous P-MBIST
Yasha Jyothi M Shirur, Bilure Chetana Bhimashankar, Veena S. Chakravarthi · 2015
In today's VLSI world, the designers concentrate on low power design, neglecting the test methodology. Defining low power test methodology is the need of the day. In this paper, Microcode based Asynchronous P-MBIST is implemented, measured and compared with similar feature Synchronous PMBIST. The implemented core has given Power, Area advantage of 95.44%, 23.95% respectively but with increased Timing of 10.04% over Synchronous P-MBIST. The design is a synthesizable core which can be extended to multiple memory fault testing. The implemented design is synthesized over two different technology 180nm & 45nm. Even, the methodology adopted has given power advantage in scaled down technology.