Research and implementation of a high speed test generation for ultra large scale combinational circuits
Zhide Zeng, Jihua Chen, Hefeng Cao · 2003
In this paper a high-speed test generation method for ultra large scale combinational circuits and full-scan circuits is presented. This method adopts the finite backtracking test pattern generation method to generate test pattern, and uses the parallel-pattern single-fault propagating method with n (machine word length) test vectors to validate the fault coverage. The test generation and fault simulation are integrated with n to 1 tightly coupled mode. The method obtains desired results: shorter test pattern length, higher fault coverage and efficiency from execution of 10 ISCAS-85 benchmark circuits.