Cache-Conscious Copying Collectors
Henry G. Baker · 2006
Garbage collectors must minimize the scarce resources of cache space and off-chip communications bandwidth to optimize performance on modern single-chip computer architectures. Strategies for achieving these goals in the context of copying garbage collection are discussed. A multi-processor mutator/collector system is analyzed. Finally, the Intel 80860XP architecture is studied. 1. Introduction. The ubiquity of on-chip caches in modern processor architectures is forced by the increasing latency of on-chip memory relative to off-chip memory. Unfortunately, this latency is also accompanied by the restricted bandwidth of small pin-outs. As a result, the management of on-chip memory space and off-chip communications traffic has become the major problem in gaining fast execution times on these processors. Lam et al [Lam91] graphically demonstrate this issue for the problem of multiplying large matrices, where the measured performance of one processor was increased from 0.9 MFLOPS to 4 MFL...