Test cost reduction by at-speed BISR for embedded DRAMs
Yoshihiro Nagura, M. Mullins, A. Sauvageau, Yoshinori Fujiwara, Katsuya Furue, Ren Ohmura, T. Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi DOSAKA, K. Arimito, Yukiyoshi Koda, Tetsuo Tada · 2002
The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SoC) device test. This paper proposes putting the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7 mm/sup 2/, about 2% of conventional SoC devices. Using an error storage table form contributes to realizing a small area penalty of the repair analysis function. e-DRAM functional test time was reduced about 20% less than the conventional method at wafer level testing. Moreover, the results of e-DRAM test and repair analysis using BISR is almost coincident with the conventional method.