Universal test set generation for CMOS circuits
B. Chen, C.L. Lee · 2002
In this paper, a fast algorithm to generate universal test set for CMOS circuits is presented. The algorithm generates the tests directly by Shannon-expanding and complementing the function, instead of the truth table enumeration. Experimental results show that this algorithm achieves an improvement of 2-6 orders of magnitude in computation efficiency and a saving of 1/spl sim/2000 fold for test-storing over the method of truth table enumeration.>