A novel structure for digital image stabilizer
Guanrong Chen, Y.-J. Yeh, Sheng‐Jyh Wang, Huang-Cheng Chiang · 2002
In this paper a new architecture for digital image stabilizer (DIS) is presented. The system utilizes a matching algorithm on the Gray-coded bit-plane of the video sequence, which greatly reduces the complexity and enables the real-time processing capability in its motion estimating mechanism. According to the algorithm, a flexible system architecture containing software and hardware blocks is proposed. The proposed design is computationally efficient and is thus well suited as a low-cost solution for DIS in camcorders. In practice, the system has been validated on a mixed FPGA/DSP-based prototype.