Fast and low-power inner product processor
N. Kazakova, Rae Cho Sung, N.G. Durdle, Martin Margala, Julien Lamoureux · 2002
This paper describes a novel fast and low-power two's complement fixed-point inner product processor targeted for 3D volume rendering applications. The design was simulated and fabricated in a 0.18 /spl mu/m, six-metal, single-poly CMOS process. Speed and power optimizations were achieved at both the architecture and circuit levels. The inner product operation, consisting of multiplications and additions, is merged into a composite function in order to minimize circuit area, improve speed and minimize power dissipation. Individual functional blocks including the partial product: encoder, reduction tree and final two operand adder were built entirely using complementary pass transistor logic (CPL) with reduced swing internal nodes to minimize the energy required during switching. Simulated results for a (8/spl times/8/spl times/8)-b implementation showed an average evaluation time of 2.6 ns at 1.8 V. The average power dissipation at 200 MHz was 2.53 mW.