VirtualScan: a new compressed scan technology for test cost reduction
L.-T. Wang, Xiaoqing Wen, H. Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai, Khader S. Abdel-Hafez, Shianling Wu · 2005
This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.