Synthetic Benchmark Generator for the MOLEN Processor
Stephan Wong, Guanzhou Luo · 2002
Most of current embedded processor designs utilize programmable processor cores augmented with specialized hardwired units. Recently, we are witnessing a shift in this design methodology towards the utilization of reconfigurable hardware (e.g., field-programmable gate arrays (FPGAs)) instead of fixed hardware. In this light, the MOLEN processor has been proposed that employs reconfigurable microcode (#-code) to control both the reconfiguration and execution processes of the reconfigurable hardware. The #-code is an extension to the traditional microcode which includes support for reconfigurable hardware. In this paper, we propose an extension to the generally accepted hardware/software co-design methodology that accomplishes the intended augmentation of reconfigurable hardware to programmable processors. Additionally, the utilization of #-code requires on-chip storage for which the storage size, the organization, and other design parameters must be investigated. To this end, we propose to generate synthetic #-code that only exhibit those characteristics that are relevant in the mentioned investigation.