A reconfigurable recursive and efficient hardware for Karatsuba-Ofman's multiplication algorithm
Nadia Nedjah, Luiza de Macedo Mourelle · 2004
Multiplication of long integers is a cornerstone primitive in most public-key cryptosystems. Multiplication for big numbers can be performed best using Karatsuba-Ofman's divide-and-conquer approach. We propose a recursive and efficient hardware for Karatsuba-Ofman's multiplication algorithm. The hardware is efficient in terms of response time and fairly compact in terms of hardware description language VHDL. The performance of the synthesised hardware in terms of time and area requirements is compared with that of Synopsys/spl trade/ library multiplier as well as two different multipliers that implement Booth's algorithm. The proposed hardware multiplies faster that the other three. However, it requires more hardware area. Nevertheless our design improves the area/spl times/time product as well as time requirement while the other three improve area at the expense of both time requirement and the factor area/spl times/time.