TIME OPTIMIZED FIXED POINT ALGORITHM FOR UNSIGNED DIVISION OPERATION IN PROGRAMMABLE LOGICAL DEVICES
Boyko Baev Petrov · 2004
The division operation is one of the basic arithmetical operations. Unfortunately, the known hardware description languages HDL such as ABEL, Cupl, VHDL and Verilog don’t support this operation in their common libraries. For many applications such as linear interpolation and linear approximation there is a necessary to use division of two signed or unsigned integer operands. The known method “pipeline divider” is designed by pipeline architecture and it has a latency time depend of the length of input operands. In many applications this latency time is unacceptable. To make division between x (dividend) and (divisor) is equal to find a new value ,