Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage
Chih-Chang Hsieh, Hang-Ting Lue, Yung Chun Li, Kuo-Ping Chang, Hsing Chen Lu, Hsiang-Pang Li, Wei-Chen Chen, Yi‐Hsuan Hsiao, Shuo-Nan Hung, Ti-Wen Chen, Yen-Hao Shih, Chih-Yuan Lu · Symposium on VLSI Technology · 2013
Multi-level cell (MLC) programming is of crucial importance to make a cost competitive NAND Flash product. In conventional 2D floating gate NAND Flash, the interference and disturb become very severe as technology scales, and many methods have been adopted to alleviate the interferences. In 3D NAND, the pitch is generally larger and the charge-trapping device naturally has smaller interference. However, disturb and interference now come from three dimensions and new understanding of device properties must be gained in order to achieve MLC operation.