Microarchitecture of HaL's memory management unit
D.C.-W. Chang, Douglas A. Lyon, C. Chen, Lin Peng, Mehran Massoumi, M. Hakimi, Satish Iyengar, Enlai Li, R. Remedios · 2002
This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.