Systolic processor array for radar and communications
Raymond J. Lackey, Herbert F. Baurle, John Barile · 2003
A systolic processor applicable to a general class of signal processing problems was built using commercially available VLSI floating-point processors. This processor performed over 1.25 BFLOPS (billion floating-point operations per second) in applications of solutions to a group of simultaneous equations with 12 unknowns. The solution was designed to work with the normal equations used in signal processing problems where all equations have noisy component values. The processor design was a direct implementation of algorithm mathematics in hardware and achieved a high processing rate through extensive concurrency. This program demonstrated how a custom, application-specific processor can be developed in less than two years to perform a computationally intensive function.>