A methodology and framework to assist in the architecture design and functional verification of complex electronic systems.
K. Tomasena-Arriaga, I. Velez-Isasmendi, Juan Sevillano Berasategui · Deposito Adademico Digital Universidad De Navarra (University of Navarra) · 2013
An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed efficiently early in the development process by means the proposed contributions.