A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations
A. Rao, Th. Haniotakis, Yiorgos E. Tsiatouhas, V. Kaky · International On-Line Testing Symposium · 2004
The use of a fault model that handles transistor level faults liketransistor stuck-open and transistor stuck-on is highly desirable inmodern designs. Unfortunately, in the case of self-checkingcheckers exploited for on-line testing the requirements of usingpairs of test vectors or special circuits for I{DDQ} monitoring may notbe applicable. A variation of the dynamic circuit design technique,which uses multiple clocks to construct three phase logicstructures, is presented that it is capable to cover the above faultmodels. The proposed technique results in checker designs thatcombine high operating frequency and reduced area requirementswhile are capable of satisfying the required self-checking andfault-secure properties. Two-rail code checker designs arepresented to demonstrate the proposed technique.