Predicting Worst Case Execution Times on a Pipelined RISC Processor
Shaun J. Bharrat, Kevin Jeffay · 1995
: A key step in analyzing and reasoning about the performance of realtime systems is the derivation of the worst case execution time of a program or program fragment. Modern computer systems with pipelined processors, caches, DMA, etc., can complicate this process. We demonstrate that pipelining need not be considered to be a barrier to the computation of useful worst case execution time bounds of programs by developing a simple method for accounting for the speed-up due to pipelining in an implementation of the Sparc RISC processor architecture. The method is applied to several non-trivial program fragments and is capable of accurately measuring worst case execution time even when programs are delayed by interrupt processing. 1. Introduction The correctness of real-time systems depends on the satisfaction of both logical and temporal constraints. An important component of evaluating whether a program meets its temporal constraints is prediction of the execution time of the entire prog...