Access time and energy tradeoffs for caches in high frequency microprocessors
Eugene B John, S. Petko, Lizy K. John, J. Law · 2003
This paper investigates the cache sizes and configurations that can be supported by a high frequency processor of the next generation. Based on the SIA roadmap prediction that a 0.1 /spl mu/m processor of the next generation will run at 3.5 GHz, we model caches of that technology using the CACTI tool. Access times as well as energy consumption are modeled for caches in the 8 K-4 M range, for various associativities. Impact of having multiple ports as well as that of varying block sizes is also studied.