Low-power CMOS circuits for analog VLSI programmable neural networks
Mohammed Abo Elsoud, Roshdy A. Abdelrassoul, Hassan Soliman, Laila El-ghanam · 2003
This paper presents an analog VLSI neural network for designing a programmable neural system. Synaptic weights are designed in the triode region using four-MOS transistors. Moreover, the summing element (SE) and the activation function are designed in subthreshold region. This system is realized in a standard 0.8 /spl mu/m CMOS technology and operated with a /spl plusmn/1V power supply.