FPGA-accelerated complex event processing
Takashi Takenaka, Hiroaki Inoue, Takeo Hosomi, Yuichi Nakamura · 2015
This paper introduces an example of real-time “big data” processing systems accelerated by field-programmable gate arrays (FPGAs), which will open up a novel design field for digital circuit engineers. Contrary to the perception that software on commodity servers dominates such large-scale processing requirements, there are various chances for utilizing hardware for the acceleration. One of the most promising applications is complex event processing (CEP), which requires hardware-based acceleration due to it having to process massive amounts of data in real time. We propose a design flow for compiling software-oriented event language into highly parallelized and pipelined CEP circuits, which enables our system to achieve a strikingly high performance of 20 Gbps. A sophisticated mechanism for integrating archives of previously arrived data with streams of current events also makes the FPGA-accelerated processing system applicable to a wide range of realistic “big data” applications.