Architecture of high performance integrated Prolog processor IPP
S. Yamaguchi, Tadaaki Bandoh, K. Kurosawa, M. Morioka · Fall joint computer conference · 1987
This paper describes a high speed integrated Prolog processor (IPP) which integrates the extended Warren's Prolog instructions, and its acceleration hardware into a 32-bit super-minicomputer. Tagged data format and instruction format under constraints of a general purpose machine architecture, and aspects of the hardware architecture of the IPP which includes some special hardware for an accelerating Prolog instruction execution are described.The IPP is implemented by high speed ECL(emitter coupled logic) gate arrays and its inference performance is 1 MLIPS for the deterministic concatenate program.It is easy for the IPP to link Prolog programs and existing procedural programs. And it can share its hardware resource with a base machine. Therefore, using the IPP, a high cost/performance practical AI system can be realized.