A 200 MHz 256 kB second level cache with 1.6 GB/s data bandwidth
D. DiMarco, M. Balmer, C. Freeman, K. Hose, Jeffrey L. Miller, E. Riggs · 2002
Improvements in processor performance have given rise to tightly-coupled, high-bandwidth second-level caches that are key to processor performance. This paper describes a 256 kB, 4-way set-associative companion cache SRAM to a microprocessor. High speed is achieved by keeping the processor and cache in the same 2-chip module and by communicating over a private 72 b data bus. Supply voltage is 3.3 V and maximum power is 3.8 W at 150 MHz, assuming back-to-back reads. The BiCMOS process features 4-level metal and 0.4 /spl mu/m Leff.