A single-chip lossless data compressor
B.W.Y. Wei, Jingwoan Chang, V.I. Leong · 2002
This paper describes a single-chip compressor implementing a combined LZSS and Huffman compression algorithm. The chip uses a 512-byte on-chip CAM/SRAM for storing the most recent characters which the incoming string is compared against and referenced to. The reference entries are then Huffman coded using a transposition implementation. The chip in 1.2 /spl mu/m CMOS is 0.9 cm/sup 2/ with a clock speed of 40 ns. With a compression ratio of above 2.1, it performs compression/decompression at a rate of 32 bytes per 33 clock cycles.