New design using a VHDL description for DCT based circuits
Mohamed Ali Benayed, Laurent Dulau, Patrice Nouel, Y. Berthournieu, Nouri Masmoudi, Patrice Kadionik, Lotfi Kamoun · 2002
This paper presents a new method to implement the DCT algorithm for JPEG or MPEG compression using VHDL description in ASIC or FPGA circuits. Discrete Cosine Transform (DCT) is one of the most popular lossy techniques used today in video compression schemes. Several algorithms have been proposed to implement the DCT. Loeffler (1989) has given a new class of 1D-DCT using just 11 multiplications and 29 additions. To implement such an algorithm, one or more multipliers have to be integrated. This requires a high silicon occupation area. Arithmetic distribution is widely used for such algorithms. However, its direct implementation requires an important silicon occupation area due to the ROM size needed. This paper presents a new technique based on the fusion of distributed arithmetic with Loeffler's algorithm to over come the above problems. We present a 1D-DCT design. This circuit has been implemented in Xilinx FPGAs.